1. Field of the Invention
This invention relates to semiconductor devices and relates more especially to MNOS transistor devices.
2. Description of the Prior Art
It is known that the MNOS transistor can be operated as a non-volatile memory in two ways, distinguished by the means of carrying out the erase function. The erase function is that phase of the operational sequence during which the selected portion of the memory array has all bits set into the "0" state. For p-channel devices, which form the basis of this example, the "0" is the state with the most positive threshold voltage and which, as a result, is the conducting state during read. A similar situation holds for n-channel devices if the polarities are changed.
Conventionally erase is achieved by applying a sufficiently large voltage between the gate and substrate such that the gate is positive with respect to the substrate. In the punch through erase mode, erase is achieved by biasing the source and drain to a sufficiently large voltage, negative with respect to both gate and substrate. Typically, the gate and substrate are both grounded. For example, see the article entitled "A New, Nonvolatile Read Write Random Access Memory Operation By Means Of Avalanche-Tunnel Injection In MNOS Transistor," by Uchida et al, Proceedings of the 4th Conference on Solid State Devices (Tokyo, 1972), Supplement to the Journal of the Japan Society of Applied Physics, Vol. 42, 1973, Section 5-2 (pages 151-157), which sets forth a typical punch through erase mode of operation.
The advantage of the conventional approach is that the memory cell is a single transistor. The disadvantage is that the transistors must be in isolated lands which makes the technology more complex and more costly. The advantage of punch through erase is that it uses the simple low cost non-isolated technology. The disadvantage is that it requires a three transistor cell.
A memory circuit consisting of an array of MNOS transistors or an array of three transistor cells is operated in the following way. First, all bits in a selected word are simultaneously erased to the "0" state by either the conventional or punch through method. This is followed by a write operation during which a negative voltage is applied to the gate. Any transistor in the word which has its source and drain at ground has its threshold shifted to the "1" or most negative state. Any transistor in the word which has its source and drain at an intermediate negative potential will experience a reduced shift of threshold. If the source and drain potential is close to that of the gate during write, the threshold shift is small and the transistor remains in the "0" state. Thus the source and drain potential is used during write to determine which bits are programmed into the "1" state and which remain in the "0" state. Finally, during read, a voltage is applied to the gate so as to turn on those devices which are in the "0" state but not those in the "1" state. This sequence can be summarised as erase, write or write inhibit, read.
The erase may be brought about by either the conventional or punch through method.